Intel's data-operand-independent-timing contract (DOITM), row by row, transcribed from Intel's list.

Source

Intel, Data Operand Independent Timing Instructions, document ID 768547, updated 2026-02-23, Table 1 "Documented Data Operand Independent Timing Instructions" (840 mnemonic/opcode rows, 594 distinct mnemonics), retrieved 2026-10-27 from www.intel.com under /content/www/us/en/developer/articles/technical/ software-security-guidance/resources/, saved from a browser (the host refuses automated retrieval; sha256 of the page as saved 0f67179a44c9f872ab240c3363ee664340beea36ce4a07cbfe1a34cc7adb6a10). The revision of 2023-02-28, as the Internet Archive kept it through 2025-11-13, lacks BSWAP, CQO, MOVAPS, MOVSS, MOVUPS, ROL, ROR, RORX, SHLD, SHRD, and XORPS; this one adds them and drops none.

Rule

A row names a mnemonic and an opcode byte: the instruction's last opcode byte, after any prefixes, VEX or EVEX payload, and escape bytes. The list's own preface reads:

The table below lists instructions that have data-independent
timing. [...] Note that these data operand independent timing
instructions may have variable latency for reasons unrelated to
the data values (for example, loading data from memory or the
encoding of the instruction).

The REP_ rows carry a footnote, "These REP_ instructions' latency varies based on the loop count (*CX)", whose marker is dropped from their names here: a count that depends on the secret repeats the instruction a different number of times, which is control flow.